In many applications it is necessary to synchronize an arbitrary first signal to a phase reference, such as an independently supplied second signal. In some cases this independently supplied second signal is a single "one-shot" signal, or occurs infrequently relative to the frequency of the first signal. For example, a high-speed video dot clock used in a high-resolution digital CRT display needs to be synchronized to the start of each video line. The start of each video line is identified by a line sync signal. However, this line sync signal may repeat only once for every thousand cycles of the video dot clock. Thus, for pratical purposes, the line sync signal in this example is effectively an asynchronous single event.
The prior art accomplishes synchronization of a first signal with a second signal typically by one of two techniques. The first technique involves the use of a local clock having a frequency that is a large multiple of the frequency of the first signal, or clock, to be synchronized. The high-frequency multiple is supplied to a divider which is reset by the occurrence of the synchronizing second signal. The problem with this technique is the necessity of using a local clock having a much higher frequency than the frequency of the clock signal to be synchronized. Thus, for very high data frequencies, the cost of a local clock operating at large multiples of that high data frequency becomes prohibitive.
The second technique is the phase-locked loop frequency multiplier often used for systems having regularly spaced synchronizing signals. The phase-locked loop frequency multiplier operates by the use of a phase detector which detects the phase of the output of a divider that divides the frequency of the clock to be synchronized to match the frequency of the synchronizing signal and compares the divided output with the phase of the synchronizing signal. A phase correction signal is generated and supplied to a voltage-controlled oscillator which adjusts the clock to be synchronized to match the synchronizing signal. The clock signal output of the voltage-controlled oscillator is supplied to the divider which is fed back to the phase detector for comparison again with the synchronizing signal. Problems with phase-locked loop systems include the fact that it takes several synchronizing events for the phase-locked loop to lock up on the correct frequency. Also, phase-locked loops suffer stability problems when there are irregular or infrequent synchronizing events with respect to the frequency of the clock to be synchronized. In the high-frequency video dot clock example, discussed above, or other systems where the occurrence of the synchronizing signal might be considered an irregular or infrequent event, the phase-locked loop would be severely prone to degradation by jitter.